/*
 * @Author: LVGRAPE
 * @LastEditors: LVGRAPE
 */
#include "drv_pin.h"
#include "drv_spi.h"



void spi2_dma_config(void)
{

    dma_init_type dma_init_struct;

    /* enable dma2 clock */
    crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);

    /* dma2 channel6 for spi2 tx configuration */
    dma_reset(DMA2_CHANNEL6);
    dma_default_para_init(&dma_init_struct);
    dma_init_struct.buffer_size = 0;
    dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
    dma_init_struct.memory_base_addr = (uint32_t)0;
    dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
    dma_init_struct.memory_inc_enable = TRUE;
    dma_init_struct.peripheral_base_addr = (uint32_t)&SPI2->dt;
    dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
    dma_init_struct.peripheral_inc_enable = FALSE;
    dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
    dma_init_struct.loop_mode_enable = FALSE;
    dma_init(DMA2_CHANNEL6, &dma_init_struct);

    /* dma1 channel3 for usart1 rx configuration */
    dma_reset(DMA2_CHANNEL7);
    dma_default_para_init(&dma_init_struct);
    dma_init_struct.buffer_size = 0;
    dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
    dma_init_struct.memory_base_addr = (uint32_t)0;
    dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
    dma_init_struct.memory_inc_enable = TRUE;
    dma_init_struct.peripheral_base_addr = (uint32_t)&SPI2->dt;
    dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
    dma_init_struct.peripheral_inc_enable = FALSE;
    dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
    dma_init_struct.loop_mode_enable = FALSE;
    dma_init(DMA2_CHANNEL7, &dma_init_struct);

    /* enable transfer full data interrupt */
    /* enable transfer full data interrupt */
    dma_interrupt_enable(DMA2_CHANNEL6, DMA_FDT_INT, TRUE);
    dma_interrupt_enable(DMA2_CHANNEL7, DMA_FDT_INT, TRUE);

    /* config flexible dma2 for spi tx */
    dma_flexible_config(DMA2, FLEX_CHANNEL6, DMA_FLEXIBLE_SPI2_TX);
    dma_flexible_config(DMA2, FLEX_CHANNEL7, DMA_FLEXIBLE_SPI2_RX);
    /* config flexible dma for usart2 rx */
    // dma_flexible_config(DMA1, FLEX_CHANNEL3, DMA_FLEXIBLE_UART1_RX);

    dma_channel_enable(DMA2_CHANNEL6, TRUE); /* usart1 rx begin dma receiving */
    dma_channel_enable(DMA2_CHANNEL7, TRUE); /* usart1 rx begin dma receiving */
    /* dma1 channel1 interrupt nvic init */
    nvic_irq_enable(DMA2_Channel6_7_IRQn, 0, 0);

    spi_i2s_dma_receiver_enable(SPI2, TRUE);
    spi_i2s_dma_transmitter_enable(SPI2, TRUE);
}
